1. Technical Field of the Invention
The present invention relates to a process for forming, on a common semiconductor substrate, a number of components, among which include CMOS transistors, vertical or lateral drain-extension MOS transistors, and LDMOS (Lateral Double-diffused MOS) transistors, in particular by dedicated silicidation techniques.
Although not limited thereto, the invention relates, in particular, to a process for forming CMOS transistors by a self-aligned silicidation technique to form source and drain active areas and low-resistance polysilicon gate electrodes, and for forming drain-extension MOS transistors with a gate region which is silicided by means of a different technique. The following description will cover this field of application for convenience of explanation only.
2. Description of Related Art
As it is well known, high-efficiency power transistors integrated on a silicon substrate, e.g., drain-extension MOS transistors for radio frequency power applications, are widely employed in such portable devices as mobile phones.
For these devices to perform as expected with respect to RF and power, they must be formed with dedicated processes that are complicated.
With reference to FIG. 1, a conventional drain-extension MOS transistor 1 will now be described, comprising a substrate 1, e.g., of the P+ type, on which an epitaxial layer 2, of the same species as the substrate but less doped, is formed.
A sinker region 3, of the same species as the substrate 1 but more doped, is then formed in the substrate 1 and the epitaxial layer 2.
A first N+ surface region 4 is formed between the epitaxial layer 2 and the sinker region 3. A second N+ region 5 is formed in the substrate 1.
A third, lightly doped N− region 6 is formed between the first and second region. In particular, the third region 6 lies adjacent to the second region 5, but out of contact with the first region 4. The third, lightly doped N− region 6 provides the drift region for the drain-extension MOS transistor.
A gate electrode G is formed on the layer 2, between the first and third regions 4 and 6, the electrode G being isolated by means of an oxide layer 7. The gate electrode G comprises a polysilicon layer 8 overlain by a silicide layer 9.
Conventionally, the drain-extension MOS device is provided with contacts 10, 11 and 12 to drain, body and source regions, respectively. The source contact 12 may be either provided on the back side of the substrate 1, as shown in FIG. 1, or on the body contact 11.
Drain-extension MOS devices for RF applications further require a short gate electrode G but with low resistance, thus capped with a silicide layer 9, so that devices having a high cutoff frequency (Ft) can be obtained, which reach a high oscillation frequency (fmax). The drift region 6 of such transistors, being lightly doped, can sustain a high drain voltage in power applications.
The processing of such devices is not compatible with the processes for fabricating VLSI CMOS devices in which the self-aligned silicidation technique is extensively employed to form source and drain active areas and low-resistance polysilicon gate electrodes. High-density high-performance CMOS structures can be fabricated with this technique.
A prior method for integrating CMOS transistors and drain-extension MOS transistors on the same substrate comprises additional steps for forming the MOS devices. In particular, standard dielectrics are deposited and patterned to protect the drift region from the standard silicidation technique.
While being advantageous from several points of view, this prior method has a drawback in that it significantly increases the resistivity of the gate electrode by reason of the protective layers that overlie the gate electrode reducing the amount of area that has to be covered with a silicide layer.
The underlying technical problem of this invention is to provide a process for integrating CMOS and drain-extension MOS devices, having appropriate structural and functional features so as to optimize the performance of the individual devices, thereby overcoming the limitations of prior art devices.